哪位大神能帮忙看看这个怎么解释啊
reg [31:0] time_num=32'd0;
always @(posedge clk_50M) //秒计数器，时间基准以clk为标准
begin
if(state==state_4)
if(time_num == 32'd149) //时间为3s,wait_second_time赋值为1
begin
time_num <= 32'd0;
wait_second_time<=1'd1;
end
else begin
time_num <= time_num +1'd1;
wait_second_time<=1'd0;
end
else begin
time_num <= 32'd0;
wait_second_time<=1'd0;
end
end
endmodule