LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ——包含库与程序包
ENTITY ALU is ——定义名为 ALU的实体
PORT (input,s2,s1,s0: in std_logic;
A,B: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)); ——标准逻辑型输入 input,s2,s1,s0
END ALU; 标准逻辑矢量型输出 output
ARCHITECTURE cmd OF ALU is
BEGIN ——结构体开始
PROCESS (input,s2,s1,s0)
VARIABLE cmdinputde:STD_LOGIC_VECTOR (2 DOWNTO 0);——进程内变量 cmdinputde 为标准逻辑矢量
BEGIN
cmdinputde:=s2&s1&s0;
case cmdinputde is
WHEN"000"=> ——判断输入 S2S1S0和 input 的值，根据
if input='1' then 真值表提供的功能进行表达式的赋值
output<=A+B+"0001";
else
output<=A+B;
end if;
WHEN"001"=>
if input='1' then
output<=A-B-"0001";
else
output<=A-B;
end if;
WHEN"010"=>
if input='1' then
output<=A+"0001";
else
output<=A;
end if;
WHEN"011"=>
if input='1' then
output<=A-"0001";
else
output<=A;
end if;
WHEN"100"=>output<=A and B;
WHEN"101"=>output<=A or B;
WHEN"110"=>output<=A Xor B;
WHEN"111"=>output<= NOT A;
END case;
END PROCESS; ——进程结束
END cmd; ——程序结束