module count(out,data,load,reset,clk,ep,et);
input load,reset,clk,ep,et;
input[3:0] data;
output[3:0] out;
reg[3:0] out;
always @(posedge clk or posedge reset)
begin
if(reset) out<=0;
else if(load) out<=data;
else if(ep&&et) out<=out+1;
else out<=out;
end
endmodule

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