cpu_init_crit:
         /*
          * flush v4 I/D caches
          */
         mov         r0, #0
         mcr         p15, 0, r0, c7, c7, 0         /* flush v3/v4 cache */
         mcr         p15, 0, r0, c8, c7, 0         /* flush v4 TLB */
         /*
          * disable MMU stuff and caches
          */
         mrc         p15, 0, r0, c1, c0, 0
         bic         r0, r0, #0x00002300         @ clear bits 13, 9:8 (--V- --RS)
         bic         r0, r0, #0x00000087         @ clear bits 7, 2:0 (B--- -CAM)
         orr         r0, r0, #0x00000002         @ set bit 2 (A) Align
         orr         r0, r0, #0x00001000         @ set bit 12 (I) I-Cache
         mcr         p15, 0, r0, c1, c0, 0
         /* Peri port setup */
         ldr         r0, =0x70000000
         orr         r0, r0, #0x13
             mcr         p15,0,r0,c15,c2,4        @ 256M(0x70000000-0x7fffffff)
#ifdef CONFIG_BOOT_ONENAND
         ldr         r0, =0x70000000                 @ onenand controller setup
         orr         r0, r0, #0x100000
         ldr         r1, =0x4000
         orr         r1, r1, #0xe0


         str         r1, [r0]
#ifdef CONFIG_S3C6410
         orr         r0, r0, #300                 @ disable watchdog
         mov         r1, #1
         str         r1, [r0]
         mov         r1, #0x23000000                 @ start buffer register
         orr         r1, r1, #0x30000
         orr         r1, r1, #0xc800
#else
         mov         r1, =0x20000000                 @ start buffer register
         orr         r1, r1, #0xc30000
         orr         r1, r1, #0xc800
#endif
         sub         r0, r1, #0x0400                 @ start address1 register
         ldr         r2, [r1, #0x84]                 @ ecc bypass
         orr         r2, r2, #0x100
         str         r2, [r1, #0x84]
         mov         r3, #0x0                 @ DFS, FBA
         str         r3, [r0, #0x00]
         str         r3, [r0, #0x04]                 @ select dataram for DDP as 0
         mov         r4, #0x104                 @ interrupt register


         mov         r5, #0x0002                 @ FPA, FSA
         mov         r6, #0x0800                 @ BSA
onenand_bl1_load:
         str         r5, [r0, #0x1c]                 @ save FPA, FSA
         orr         r6, r6, #0x02                 @ BSC
         str         r6, [r1, #0x00]                 @ save BSA, BSC
         str         r3, [r1, r4]                 @ clear interrupt
         str         r3, [r1, #0x80]                 @ write load command
        
         mov         r7, #0x100                 @ need small delay
onenand_wait_loop1:
         subs         r7, r7, #0x1
         bne         onenand_wait_loop1
         add         r5, r5, #0x2                 @ next FPA, FSA
         sub         r6, r6, #0x2
         add         r6, r6, #0x200                 @ next BSA
         cmp         r5, #0x8
         bne         onenand_bl1_load
#endif
这里是s3c6410的u-boot启动代码start.S里的一些代码，其中不解的是
#ifdef CONFIG_S3C6410
         orr         r0, r0, #300                 @ disable watchdog
         mov         r1, #1
         str         r1, [r0]
这里关闭看门狗的设置，这里的r0所存的地址应该是0x7010012c,而s3c6410手册中的看门狗的定时控制器的地址应该是0x7E004000，这里是怎么设置看门狗的
还有就是str         r3, [r0, #0x04]                 @ select dataram for DDP as 0这句指的是什么意思
刚刚看这个东西 很多东西都不太理解 希望大侠们能指导指导   谢谢了……