有没有大神帮帮孩子啊 用VHDL语言

entity encoder8to3
port(
I : in std_logic_vector(7 downto 0);
A : out std_logic_vector(2 downto 0)
);
end encoder8to3;
architecture rtl of encoder8to3 is
begin
process(I)
begin
if(I(0) = '1') then
A <= "111";
end if;
end process;
end rtl;
优先级编码器，剩下的我就不写了