module mydds(
DATA,
WE_F,
CLKP,
CE,
ACLR,
SINE,
COSINE
);
input[31 : 0] DATA;
input WE_F,CLKP,CE,ACLR;
output[15 : 0] SINE;
output[15 : 0] COSINE;
parameter DATA_DEF=32'H51EB851;
reg[31:0] ADD_A, ADD_B;
wire[31:0] DATA;
always @(posedge CLKP or posedge ACLR)
if(ACLR) ADD_A<=DATA_DEF;
else if(WE_F) ADD_A<=DATA;
always @(posedge CLKP or posedge ACLR)
if(ACLR) ADD_B<=0;
else if(CE) ADD_B<=ADD_B+ADD_A;
wire[10:0] ROM_A;
assign ROM_A=ADD_B[31:21];
wire[15:0] COS_D;
rom_cos cos(
.addr(ROM_A),
.clk(CLKP),
.dout(COS_D),
.en(CE));
reg[15:0] COS_DR;
always @(posedge CLKP, posedge ACLR)
if(ACLR) COS_DR<=0;
else if(CE) COS_DR<=COS_D;
assign COSINE = COS_DR;
wire[15:0] SIN_D;
rom_sin sin(
.addr(ROM_A),
.clk(CLKP),
.dout(SIN_D),
.en(CE));
reg[15:0] SIN_DR;
always @(posedge CLKP or posedge ACLR)
if(ACLR) SIN_DR<=0;
else if(CE)SIN_DR<=SIN_D;
assign SINE = SIN_DR;
endmodule