主程序
module NCO(
dac_sclk,
dac_din,
dac_csn,
clk,
rst
);
output dac_sclk,dac_din,dac_csn;
input clk,rst;wire rst_n;
wire inclk;
wire pll_rst;PLL PLL1 (
.areset(pll_rst),
.inclk0(clk),
.c0(inclk),
.locked(rst_n)
);wire [11:0]data_1;
wire [11:0]data_2;
nco_test nco_test1 (
.clk(inclk),
.clken(rst_n),
.phi_inc_i(32'd429496),
.freq_mod_i(32'd429496),
.phase_mod_i(16'd65535),
.fsin_o(data_1),
.fcos_o(),
.out_valid(),
.reset_n(rst_n)
);
tlv5618a_device tlv5618a_device1(
.DATA_A(data_2),
.DATA_B(12'b010_0000),
.clk(inclk),
.rst(rst_n),
.dac_sclk(dac_sclk),
.dac_din(dac_din),
.dac_csn(dac_csn)
);
assign data_2 = data_1 + 12'd2048;
assign pll_rst = ~rst;
endmodule
testbench程序
`timescale 1ns/1ns
module NCO_tb();
wire dac_sclk,dac_din,dac_csn;
reg clk,rst;NCO NCO1(
.dac_sclk(dac_sclk),
.dac_din(dac_din),
.dac_csn(dac_csn),
.clk(clk),
.rst(rst)
);
initial begin
clk <= 0;
rst <=0;
end
always #10 clk <= ~clk;initial begin
#100;
rst <= 0;
#100;
rst <=1;
#100000000;
end
endmodule

据说可能是pll.areset那边有问题， 模块运行时，rst信号为低，给pll.areset输入为高，pll被reset了