Error (10200): Verilog HDL Conditional Statement error at try1.v(146): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

always @(posedge clk or negedge rst)
begin
if(error11>32'b00000001010000000000000000000000) //>20
begin
error1 <= 32'b00000001010000000000000000000000; //对输出进行限幅20
end
else
if(error11<32'b10000001010000000000000000000000) //<-20
begin
error1 <= 32'b10000001010000000000000000000000; //对输出进行限幅-20
end
else
begin
error1<=error11;
end
end

1.rst没有写，if（！rst）
2.信号命名没有含义，可读性差。
3.不要用二进制，尤其这么大的位宽，容易出错也不好排查。建议用32'h