library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity zhuanhuan is
port(x0,x1,x2,x3:in std_logic;clk:in std_logic;y0,y1,y2,y3:out std_logic);
end zhuanhuan;
architecture bhv of zhuanhuan is
signal x:std_logic_vector(3 downto 0);
signal d:std_logic_vector(3 downto 0);
signal seg_y:std_logic_vector(3 downto 0);
begin
process(x)
begin
x<=x0&x1&x2&x3;
IF(clk='1')
then case(x) is
when"0001"=>y<='1';
when"0010"=>y<='2';
when"0011"=>y<='3';
when"0100"=>y<='4';
when"0101"=>y<='5';
when"0110"=>y<='6';
when"0111"=>y<='7';
when"1000"=>y<='8';
when"1001"=>y<='9';
when"others"=>y<='0';
end case;
end if;
end process;
process(clk1)
begin
if(clk'event and clk='1')
then d<=d+1;
end if;
end process;
process(d)
begin
case d is
when y"0"=> seg_y<=y"c0"；
when y"1"=> seg_y<=y"f9";
when y"2"=> seg_y<=y"a4";
when y"3"=> seg_r<=y"b0";
when y"4"=> seg_y<=y"99";
when y"5"=> seg_y<=y"92";
when y"6"=> seg_y<=y"82";
when y"7"=> seg_y<=y"f8";
when y"8"=> seg_y<=y"80";
when y"9"=> seg_y<=y"90";
when others=> seg_y<=y"ff";
end case;
end process;
y<=seg_y;
end;
Error (10500): VHDL syntax error at zhuanhuan.vhd(41) near text ""c0""; expecting ";"
Error (10500): VHDL syntax error at zhuanhuan.vhd(42) near text ""f9""; expecting ";"
Error (10500): VHDL syntax error at zhuanhuan.vhd(43) near text ""a4""; expecting ";"
Error (10500): VHDL syntax error at zhuanhuan.vhd(44) near text ""b0""; expecting ";"
Error (10500): VHDL syntax error at zhuanhuan.vhd(45) near text ""99""; expecting ";"
Error (10500): VHDL syntax error at zhuanhuan.vhd(46) near text ""92""; expecting ";"
Error (10500): VHDL syntax error at zhuanhuan.vhd(47) near text ""82""; expecting ";"
Error (10500): VHDL syntax error at zhuanhuan.vhd(48) near text ""f8""; expecting ";"