module yyy(iST_A,iSTB_N,iSTC_N,iA,oY1,oY2,s);
input iST_A,iSTB_N,iSTC_N;
input [3:0]iA;
output [7:0]oY1,[7:0]oY2;
output s;
reg [7:0]m_y1,[7:0]m_y2;
assign oY1=m_y1,oY2=m_y2;
if(!iA[3])
always@(iSTB_N,iSTC_N,iA)
begin
if(!(iSTB_N||iSTC_N))
case(iA)
4'b0000:oY1 = 8'b11111110;
4'b0001:oY1 = 8'b11111101;
4'b0010:oY1 = 8'b11111011;
4'b0011:oY1 = 8'b11110111;
4'b0100:oY1 = 8'b11101111;
4'b0101:oY1 = 8'b11011111;
4'b0110:oY1 = 8'b10111111;
4'b0111:oY1 = 8'b01111111;
endcase
else
oY1=8'h11111111;
end
else
always@(iSTB_N,iSTC_N,iA)
if(!(iSTB_N||iSTC_N))
case(iA)
4'b10000:oY2 = 8'b11111110;
4'b10001:oY2 = 8'b11111101;
4'b10010:oY2 = 8'b11111011;
4'b10011:oY2 = 8'b11110111;
4'b10100:oY2 = 8'b11101111;
4'b10101:oY2 = 8'b11011111;
4'b10110:oY2 = 8'b10111111;
4'b10111:oY2 = 8'b01111111;
endcase
else
oY2=8'h11111111;
assign
s = ~((~y1[7])&(~y2[1])&(~y2[2])&(~y2[3])&(~y2[4])&(~y2[5])&(~y2[6])&(~y2[7]));
endmodule
错误是：

Error (10112): Ignored design unit "yyy" at yyy.v(1) due to previous errors
Info: Found 0 design units, including 0 entities, in source file yyy.v
Error: Quartus II Analysis & Synthesis was unsuccessful. 6 errors, 9 warnings
Error: Peak virtual memory: 239 megabytes
Error: Processing ended: Sun Apr 23 11:25:01 2017
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:00
Error: Quartus II Full Compilation was unsuccessful. 8 errors, 9 warnings