level 2
自己仿真WAIT FOR语句出现错误,知道综合语句不能用WAIT FOR,但不知怎么仿真。能贴出两个仿真图最好。程序如下
2017年01月16日 07点01分
1
level 2
1.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TBCTRLS_vhd IS
END TBCTRLS_vhd;
ARCHITECTURE behavior OF TBCTRLS_vhd IS
COMPONENT CTRLS
PORT(CLK : IN std_logic;
SEL : OUT std_logic_vector(2 downto 0));
END COMPONENT;
SIGNAL CLK : std_logic := '0';
SIGNAL SEL : std_logic_vector(2 downto 0);
BEGIN
uut: CTRLS PORT MAP(
CLK => CLK,
SEL => SEL);
tb : PROCESS
BEGIN
CLK<='0';
WAIT FOR 100 NS;
CLK<='1';
WAIT FOR 100 NS;
END PROCESS;
END;
2017年01月16日 07点01分
2
level 2
2.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tbb_vhd IS
END tbb_vhd;
ARCHITECTURE behavior OF tbb_vhd IS
COMPONENT fenpinqi
PORT(clk : IN std_logic;
clkout1 : OUT std_logic;
clkout10 : OUT std_logic;
clkout100 : OUT std_logic;
clkout1K : OUT std_logic);
END COMPONENT;
SIGNAL clk : std_logic := '0';
SIGNAL clkout1 : std_logic;
SIGNAL clkout10 : std_logic;
SIGNAL clkout100 : std_logic;
SIGNAL clkout1K : std_logic;
BEGIN
uut: fenpinqi PORT MAP(clk => clk,
clkout1 => clkout1,
clkout10 => clkout10,
clkout100 => clkout100,
clkout1K => clkout1K);
tb : PROCESS
BEGIN
clk<='0';
wait for 10 ps;
clk<='1';
wait for 10 ps;
END PROCESS;
END;
2017年01月16日 07点01分
3