啦啦啦 求助 大神快到碗里来

2楼

下面是用VHDL（生成语句）描述的顶层文件.
LIBRARY ieee;
• USE ieee.std_logic_1164.all;
• ENTITY test IS
• PORT(clk,di,reset:IN STD_LOGIC;
• qout:OUT STD_LOGIC );
• END;
• ARCHITECTURE bhv OF test IS
• component dffr
• PORT( clk,d,rst: IN STD_LOGIC;
• q:OUT STD_LOGIC );
• end component;
• signal tmp:STD_LOGIC_vector(0 to 3);
• signal reset0,reset1:STD_LOGIC;
• begin
• tmp(0)<=di;
• count_clk(0)<=clk;
• vcg:for i in 0 to 2 generate
• u0:dffr port map(rst=>reset0,clk=>clk,d=>tmp(i),q=>tmp(i+1));
• end generate;
• qout<= tmp(3);
• reset1<=not(tmp(2) andtmp(3));reset0<=reset and reset1;
• end;
(1) 画出对应的顶层电路原理图。
(2) 分析该电路的功能（底层元件DFFR为触发器,低电平复位）。

完全不会啊 唉