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library ieee;
use ieee.std_logic_1164.all;
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entity ssd_game2 is
port(clk,stop:in bit;
dout: out bit_vector(6 downto 0));
end ssd_game2;
-----------------------------------------
architecture fsm of ssd_game2 is
constant time1: integer:=4; --actual value need change
constant time1: integer:=2;
type states is(a,ab,b,bc,c,cd,d,de,e,ef,f,fa);
signal pst,nst:states;
signal count: integer range 0 to 5;
signal flip : bit;
begin
-----------------lower section of fsm-------------
process(clk,stop)
begin
if(stop = '1') then
pst<=a;
elsif(clk'event and clk='1') then
if((flip='1' and count=time1)or(flip='0' and count=time2)) then
count<=0;
pst<=nst;
else count<=count+1;
end if;
end if;
end process;
---------------upper section of fsm--------------
process(pst)
begin
case pst is
when a =>
dout<="1000000";
flip<='1';
nst<=ab;
when ab=>
dout<="1100000";
flip<='0';
nst<=b;
when b=>
dout<="0100000";
flip<='1';
nst<=bc;
when bc=>
dout<="0110000";
flip<='0';
nst<=c;
when c=>
dout<="0010000";
flip<='1';
nst<=cd;
when cd=>
dout<="0011000";
flip<='0';
nst<=d;
when d=>
dout<="0001000";
flip<='1';
nst<=de;
when de=>
dout<="0001100";
flip<='0';
nst<=e;
when e=>
dout<="0000100";
flip<='1';
nst<=ef;
when ef=>
dout<="0000110";
flip<='0';
nst<=f;
when f=>
dout<="0000010";
flip<='1';
nst<=fa;
when fa=>
dout<="0100000";
flip<='0';
nst<=a;
when others=>
nst<=a;
flip<='1';
--dout<=""
end case;
end process;
end fsm;
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