LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY exa4_1 IS
PORT (CLK,RST1,RST2:IN STD_LOGIC;
DOUT1,DOUT2,DOUT3,DOUT4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END exa4_1;
ARCHITECTURE fwm OF exa4_1 IS
SIGNAL Q1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Q2: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Q3: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Q4: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,RST1,RST2)
BEGIN
IF RST1='0'THEN Q1<=(OTHERS=>'0');COUT<='0';
ELSIF CLK'EVENT AND CLK='1' THEN
Q1<=Q1+1;
IF Q1>="1001" THEN Q1<=(OTHERS=>'0');Q2<=Q2+1;END IF;
IF Q2>="0001" THEN Q2<=(OTHERS=>'0');Q3<=Q3+1;END IF;
IF Q3>="1001" THEN Q3<=(OTHERS=>'0');Q4<=Q4+1;END IF;
IF Q3>="0001" AND Q4>="0001"THEN Q3<="0000" AND Q4<="0000";END IF;错误行
END IF;
END PROCESS;
DOUT1<=Q1;
END fwm;
Error (10327): VHDL error at exa4_1.vhd(24): can't determine definition of operator ""<="" -- found 0 possible definition 在线等