library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity more is
port(clk,ready,read_write: in std_logic;
reset: in std_logic;
oe,we:out std_logic
);
end more;
architecture state_machine of moore is
type state_type is(idle,decision,read,write);
signal present_state;next_state;state_type;
begin
state_comb: process(present_state;ready;read_write);
begin
case present_state is
when idle=> oe<='1';--空闲状态
we<='1';
if ready='1' then
next_state<=decision;
else
next_state<=idle;
end if;
when decision=>oe<='0';--判断状态
we<='0';
if read_write='1';
next_state<=read;
else
next_state<=write;
end if;
when read=>oe<='1';--读状态
we<='0';
if ready='1';
next_state<=idle;
else
next_state<=read;
end if;
when write=>oe<='0';--写状态
we<='1';
if ready='1' then
next_state<=idle;
else
next_state<=write;
end if;
end case;
end process state_comb;
stat_clocked:process(clk,reset)
begin
if reset='0';
present_state<=idle;
elsif rising_edge(clk) then
present_state<=next_state;
end if;
end process stat_clocked;
end state_machine;