一楼度娘

DivClock：
module DivClock(input Reset_n,input Clock_50MHz,outputreg Clk_1KHz);
reg [31:0]Counter;
parameterDELAY_NUM = 25;//_000 - 1;
always@(negedgeReset_n or posedge Clock_50MHz)
begin
if(Reset_n == 1'b0)
begin
Counter<= 0;
Clk_1KHz<= 0;
end
else
begin
Counter<= Counter + 1;
if(Counter== DELAY_NUM)
begin
Counter <= 0;
Clk_1KHz <= ~Clk_1KHz;
end
end
end
endmodule

PC：
module PC(Reset_n,Clk,OptEn,D,O);
input Reset_n;
input OptEn,Clk;
input [32:1]D;
output [32:1]O;
reg [32:1]O;
always@(negedge Reset_n or posedge Clk)
begin
if(Reset_n ==1'b0)
O<=0;
else if(OptEn== 1'b1)
O<=D;
else
O<=0;
end
endmodule

IR_Memory：
module IR_Memory(input [31:0] Addr,outputreg [31:0] Instr);
always@(*)
begin
case(Addr[6:2]) //The regular mode: Addr[31:2]; PC counter + 4 per step.
0:Instr <= 32'h0000_8020;
1:Instr <= 32'h8e13_0000;
2:Instr <= 32'hae13_0003;
3:Instr <= 32'h0800_0001;
default: Instr <=32'h0800_0000;
endcase
end
Endmodule
Control：
moduleControl(ControlCmd,RegDst,Branch,MemRead,MemtoReg,ALUOp,MemWrite,ALUSrc,RegWrite,Jump);
input[5:0]ControlCmd;
outputreg RegDst,Branch,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite,Jump;
outputreg [1:0]ALUOp;
always@(ControlCmd)
begin
case(ControlCmd)
6'b000000: //R-type
begin
RegDst= 1;
ALUSrc= 0;
MemtoReg= 0;
MemRead= 0;
MemWrite= 0;
Branch= 0;
Jump= 0;
ALUOp= 2;
RegWrite= 1;
end
6'b000010: // Jump
begin
RegDst= 0;
ALUSrc= 0;
MemtoReg= 0;
RegWrite= 0;
MemRead= 0;
MemWrite= 0;
Branch= 0;
Jump= 1;
ALUOp= 0;
end
6'b000100: // Beq
begin
RegDst= 0;
ALUSrc= 0;
MemtoReg= 0;
RegWrite= 0;
MemRead= 0;
MemWrite= 0;
Branch= 1;
Jump= 0;
ALUOp= 1;
end
6'b001000: // Addi
begin
RegDst= 0;
ALUSrc= 1;
MemtoReg= 0;
MemRead= 0;
MemWrite= 0;
Branch= 0;
Jump= 0;
ALUOp= 0;
RegWrite= 1;
end
6'b100011: // Lw
begin
RegDst= 0;
ALUSrc= 1;
MemtoReg= 1;
MemRead= 1;
MemWrite= 0;
Branch= 0;
Jump= 0;
ALUOp= 0;
RegWrite= 1;
end
6'b101011: // Sw
begin
RegDst= 0;
ALUSrc= 1;
MemtoReg= 0;
RegWrite= 0;
MemRead= 0;
Branch= 0;
Jump= 0;
ALUOp= 0;
MemWrite= 1;
end
default:;
endcase
end
endmodule

MUX_2：
module MUX_2(S,D0,D1,Out);
input S;
input [32:1]D0,D1;
output [32:1]Out;
reg [32:1]Out;
always@(*)
begin
case(S)
0:Out<=D0;
1:Out<=D1;
endcase
end
Endmodule

Registers：
moduleRegisters(Reset_n,Clock,R_num1,R_num2,R_num3,W_num,DIN,RegWrite,DOUT1,DOUT2,
DOUT3,DOUT4,DOUT5,DOUT6,DOUT7,DOUT8,
R_num4,R_num5,R_num6,R_num7,R_num8);
input Reset_n,Clock;
input [5:1]R_num1,R_num2,W_num;
input[4:0]R_num3,R_num4,R_num5,R_num6,R_num7,R_num8;
input [32:1]DIN;
input RegWrite;
output[32:1]DOUT1,DOUT2,DOUT3,DOUT4,DOUT5,DOUT6,DOUT7,DOUT8;
reg [32:1]DOUT1,DOUT2,DOUT3,DOUT4,DOUT5,DOUT6,DOUT7,DOUT8;
reg[32:1]at,v0,v1,a0,a1,a2,a3,t0,t1,t2,t3,t4,t5,t6,t7;
reg[32:1]s0,s1,s2,s3,s4,s5,s6,s7,t8,t9,k0,k1,gp,sp,fp,ra;
always@(negedge Reset_n or posedge Clock)
begin
if(Reset_n== 0)
begin
at<=0;
v0<=0;
v1<=0;
a0<=0;
a1<=0;
a2<=0;
a3<=0;
t0<=0;
t1<=0;
t2<=0;
t3<=0;
t4<=0;
t5<=0;
t6<=0;
t7<=0;
s0<=0;
s1<=0;
s2<=0;
s3<=0;
s4<=0;
s5<=0;
s6<=0;
s7<=0;
t8<=0;
t9<=0;
k0<=0;
k1<=0;
end
elseif(RegWrite)
begin
case(W_num)
5'b00001:at<=DIN;
5'b00010:v0<=DIN;
5'b00011:v1<=DIN;
5'b00100:a0<=DIN;
5'b00101:a1<=DIN;
5'b00110:a2<=DIN;
5'b00111:a3<=DIN;
5'b01000:t0<=DIN;
5'b01001:t1<=DIN;
5'b01010:t2<=DIN;
5'b01011:t3<=DIN;
5'b01100:t4<=DIN;
5'b01101:t5<=DIN;
5'b01110:t6<=DIN;
5'b01111:t7<=DIN;
5'b10000:s0<=DIN;
5'b10001:s1<=DIN;
5'b10010:s2<=DIN;
5'b10011:s3<=DIN;
5'b10100:s4<=DIN;
5'b10101:s5<=DIN;
5'b10110:s6<=DIN;
5'b10111:s7<=DIN;
5'b11000:t8<=DIN;
5'b11001:t9<=DIN;
5'b11010:k0<=DIN;
5'b11011:k1<=DIN;
default :;
endcase
end

接上一段
end
always@(*)
begin
case(R_num1)
5'b00000:DOUT1=5'H0;
5'b00001:DOUT1=at;
5'b00010:DOUT1=v0;
5'b00011:DOUT1=v1;
5'b00100:DOUT1=a0;
5'b00101:DOUT1=a1;
5'b00110:DOUT1=a2;
5'b00111:DOUT1=a3;
5'b01000:DOUT1=t0;
5'b01001:DOUT1=t1;
5'b01010:DOUT1=t2;
5'b01011:DOUT1=t3;
5'b01100:DOUT1=t4;
5'b01101:DOUT1=t5;
5'b01110:DOUT1=t6;
5'b01111:DOUT1=t7;
5'b10000:DOUT1=s0;
5'b10001:DOUT1=s1;
5'b10010:DOUT1=s2;
5'b10011:DOUT1=s3;
5'b10100:DOUT1=s4;
5'b10101:DOUT1=s5;
5'b10110:DOUT1=s6;
5'b10111:DOUT1=s7;
5'b11000:DOUT1=t8;
5'b11001:DOUT1=t9;
5'b11010:DOUT1=k0;
5'b11011:DOUT1=k1;
default :DOUT1=5'H0;
endcase
end
always@(*)
begin
case(R_num3)
5'b00000:DOUT3=32'hc0;
5'b00001:DOUT3=32'hf9; //at;
5'b00010:DOUT3=32'ha4; //v0;
5'b00011:DOUT3=32'hb0; //v1;
5'b00100:DOUT3=32'h99; //a0;
5'b00101:DOUT3=32'h92; //a1;
5'b00110:DOUT3=32'h82; //a2;
5'b00111:DOUT3=32'hf8; //a3;
5'b01000:DOUT3=32'h80; //t0;
5'b01001:DOUT3=32'h98; //t1;
5'b01010:DOUT3=t2;
5'b01011:DOUT3=t3;
5'b01100:DOUT3=t4;
5'b01101:DOUT3=t5;
5'b01110:DOUT3=t6;
5'b01111:DOUT3=t7;
5'b10000:DOUT3=s0;
5'b10001:DOUT3=s1;
5'b10010:DOUT3=s2;
5'b10011:DOUT3=s3;
5'b10100:DOUT3=s4;
5'b10101:DOUT3=s5;
5'b10110:DOUT3=s6;
5'b10111:DOUT3=s7;
5'b11000:DOUT3=t8;
5'b11001:DOUT3=t9;
5'b11010:DOUT3=k0;
5'b11011:DOUT3=k1;
default :DOUT3=5'H0;
endcase
end
always@(*)
begin
case(R_num2)
5'b00000:DOUT2=5'H0;
5'b00001:DOUT2=at;
5'b00010:DOUT2=v0;
5'b00011:DOUT2=v1;
5'b00100:DOUT2=a0;
5'b00101:DOUT2=a1;
5'b00110:DOUT2=a2;
5'b00111:DOUT2=a3;
5'b01000:DOUT2=t0;
5'b01001:DOUT2=t1;
5'b01010:DOUT2=t2;
5'b01011:DOUT2=t3;
5'b01100:DOUT2=t4;
5'b01101:DOUT2=t5;
5'b01110:DOUT2=t6;
5'b01111:DOUT2=t7;
5'b10000:DOUT2=s0;
5'b10001:DOUT2=s1;
5'b10010:DOUT2=s2;
5'b10011:DOUT2=s3;
5'b10100:DOUT2=s4;
5'b10101:DOUT2=s5;
5'b10110:DOUT2=s6;
5'b10111:DOUT2=s7;
5'b11000:DOUT2=t8;
5'b11001:DOUT2=t9;
5'b11010:DOUT2=k0;
5'b11011:DOUT2=k1;
default :DOUT2=5'H0;
endcase
end
always@(*)
begin
case(R_num3)
5'b00000:DOUT4=32'hc0;
5'b00001:DOUT4=32'hf9; //at;
5'b00010:DOUT4=32'ha4; //v0;
5'b00011:DOUT4=32'hb0; //v1;
5'b00100:DOUT4=32'h99; //a0;
5'b00101:DOUT4=32'h92; //a1;
5'b00110:DOUT4=32'h82; //a2;
5'b00111:DOUT4=32'hf8; //a3;
5'b01000:DOUT4=32'h80; //t0;
5'b01001:DOUT4=32'h98; //t1;
5'b01010:DOUT4=t2;
5'b01011:DOUT4=t3;
5'b01100:DOUT4=t4;
5'b01101:DOUT4=t5;
5'b01110:DOUT4=t6;
5'b01111:DOUT4=t7;
5'b10000:DOUT4=s0;
5'b10001:DOUT4=s1;
5'b10010:DOUT4=s2;
5'b10011:DOUT4=s3;
5'b10100:DOUT4=s4;
5'b10101:DOUT4=s5;
5'b10110:DOUT4=s6;
5'b10111:DOUT4=s7;
5'b11000:DOUT4=t8;
5'b11001:DOUT4=t9;
5'b11010:DOUT4=k0;
5'b11011:DOUT4=k1;
default :DOUT4=5'H0;
endcase
end
always@(*)
begin
case(R_num3)
5'b00000:DOUT5=32'hc0;
5'b00001:DOUT5=32'hf9; //at;
5'b00010:DOUT5=32'ha4; //v0;
5'b00011:DOUT5=32'hb0; //v1;
5'b00100:DOUT5=32'h99; //a0;
5'b00101:DOUT5=32'h92; //a1;
5'b00110:DOUT5=32'h82; //a2;
5'b00111:DOUT5=32'hf8; //a3;
5'b01000:DOUT5=32'h80; //t0;
5'b01001:DOUT5=32'h98; //t1;
5'b01010:DOUT5=t2;
5'b01011:DOUT5=t3;
5'b01100:DOUT5=t4;
5'b01101:DOUT5=t5;
5'b01110:DOUT5=t6;
5'b01111:DOUT5=t7;
5'b10000:DOUT5=s0;
5'b10001:DOUT5=s1;
5'b10010:DOUT5=s2;
5'b10011:DOUT5=s3;
5'b10100:DOUT5=s4;
5'b10101:DOUT5=s5;
5'b10110:DOUT5=s6;
5'b10111:DOUT5=s7;
5'b11000:DOUT5=t8;
5'b11001:DOUT5=t9;
5'b11010:DOUT5=k0;
5'b11011:DOUT5=k1;
default :DOUT5=5'H0;
endcase
end
always@(*)
begin
case(R_num3)
5'b00000:DOUT6=32'hc0;
5'b00001:DOUT6=32'hf9; //at;
5'b00010:DOUT6=32'ha4; //v0;
5'b00011:DOUT6=32'hb0; //v1;
5'b00100:DOUT6=32'h99; //a0;
5'b00101:DOUT6=32'h92; //a1;
5'b00110:DOUT6=32'h82; //a2;
5'b00111:DOUT6=32'hf8; //a3;
5'b01000:DOUT6=32'h80; //t0;
5'b01001:DOUT6=32'h98; //t1;
5'b01010:DOUT6=t2;
5'b01011:DOUT6=t3;
5'b01100:DOUT6=t4;
5'b01101:DOUT6=t5;
5'b01110:DOUT6=t6;
5'b01111:DOUT6=t7;
5'b10000:DOUT6=s0;
5'b10001:DOUT6=s1;
5'b10010:DOUT6=s2;
5'b10011:DOUT6=s3;
5'b10100:DOUT6=s4;
5'b10101:DOUT6=s5;
5'b10110:DOUT6=s6;
5'b10111:DOUT6=s7;
5'b11000:DOUT6=t8;
5'b11001:DOUT6=t9;
5'b11010:DOUT6=k0;
5'b11011:DOUT6=k1;
default :DOUT6=5'H0;
endcase
end
always@(*)
begin
case(R_num3)
5'b00000:DOUT7=32'hc0;
5'b00001:DOUT7=32'hf9; //at;
5'b00010:DOUT7=32'ha4; //v0;
5'b00011:DOUT7=32'hb0; //v1;
5'b00100:DOUT7=32'h99; //a0;
5'b00101:DOUT7=32'h92; //a1;
5'b00110:DOUT7=32'h82; //a2;
5'b00111:DOUT7=32'hf8; //a3;
5'b01000:DOUT7=32'h80; //t0;
5'b01001:DOUT7=32'h98; //t1;
5'b01010:DOUT7=t2;
5'b01011:DOUT7=t3;
5'b01100:DOUT7=t4;
5'b01101:DOUT7=t5;
5'b01110:DOUT7=t6;
5'b01111:DOUT7=t7;
5'b10000:DOUT7=s0;
5'b10001:DOUT7=s1;
5'b10010:DOUT7=s2;
5'b10011:DOUT7=s3;
5'b10100:DOUT7=s4;
5'b10101:DOUT7=s5;
5'b10110:DOUT7=s6;
5'b10111:DOUT7=s7;
5'b11000:DOUT7=t8;
5'b11001:DOUT7=t9;
5'b11010:DOUT7=k0;
5'b11011:DOUT7=k1;
default :DOUT7=5'H0;
endcase
end
always@(*)
begin
case(R_num3)
5'b00000:DOUT8=32'hc0;
5'b00001:DOUT8=32'hf9; //at;
5'b00010:DOUT8=32'ha4; //v0;
5'b00011:DOUT8=32'hb0; //v1;
5'b00100:DOUT8=32'h99; //a0;
5'b00101:DOUT8=32'h92; //a1;
5'b00110:DOUT8=32'h82; //a2;
5'b00111:DOUT8=32'hf8; //a3;
5'b01000:DOUT8=32'h80; //t0;
5'b01001:DOUT8=32'h98; //t1;
5'b01010:DOUT8=t2;
5'b01011:DOUT8=t3;
5'b01100:DOUT8=t4;
5'b01101:DOUT8=t5;
5'b01110:DOUT8=t6;
5'b01111:DOUT8=t7;
5'b10000:DOUT8=s0;
5'b10001:DOUT8=s1;
5'b10010:DOUT8=s2;
5'b10011:DOUT8=s3;
5'b10100:DOUT8=s4;
5'b10101:DOUT8=s5;
5'b10110:DOUT8=s6;
5'b10111:DOUT8=s7;
5'b11000:DOUT8=t8;
5'b11001:DOUT8=t9;
5'b11010:DOUT8=k0;
5'b11011:DOUT8=k1;
default :DOUT8=5'H0;
endcase
end
endmodule

SignExtended：
module SignExtended(in,out);
input [15:0]in;
output [31:0]out;
reg [31:0]out;
integer i;
always@(in)
begin
out[15:0]<=in[15:0];
for(i=16;i<32;i=i+1)
out[i]<=in[15];
end
endmodule

MUX_2：
module MUX_2(S,D0,D1,Out);
input S;
input [32:1]D0,D1;
output [32:1]Out;
reg [32:1]Out;
always@(*)
begin
case(S)
0:Out<=D0;
1:Out<=D1;
endcase
end
endmodule

ALU_Control：
module ALU_Control(Func,ALUOp,AluControl);
input [5:0] Func;
input [1:0] ALUOp;
output reg [3:0] AluControl;
always@(Func or ALUOp)
begin
case(ALUOp)
2'b00:
begin
AluControl <= 4'b0010;
end
2'b01:
begin
AluControl <= 4'b0110;
end
2'b10:
begin
case(Func)
6'b100_000:
AluControl <= 4'b0010;
6'b100_010:
AluControl <= 4'b0110;
6'b100_100:
AluControl <= 4'b0000;
6'b100_101:
AluControl <= 4'b0001;
6'b101_010:
AluControl <= 4'b0111;
default:;
endcase
end
default:;
endcase
end
endmodule

ALU：
moduleALU(ALU_op,ALU_A,ALU_B,Zero,ALU_out);
input [4:1]ALU_op;
input [32:1]ALU_A,ALU_B;
output reg Zero;
output reg [32:1]ALU_out;
always@(*)
begin
case(ALU_op)
4'b0000:
begin
ALU_out=ALU_A&ALU_B;
Zero=0;
end
4'b0001:
begin
ALU_out=ALU_A|ALU_B;
end
4'b0010:
begin
ALU_out=ALU_A+ALU_B;
Zero=0;
end
4'b0110:
begin
ALU_out=ALU_A-ALU_B;
if(ALU_out==0)
Zero=1;
else
Zero=0;
end
4'b0111:
begin
ALU_out=(ALU_A<ALU_B);
Zero=0;
end
default:
begin
ALU_out=0;
Zero=0;
end
endcase
end
Endmodule
Data_Memory：
module Data_Memory(input Reset_n,
input Clock,
input MemWrite,
input MemRead,
input [31:0]data_in,
input [31:0]addr,
input [3:0]SW_Key,
output reg [31:0]outp,
output [7:0]seg_com,
output [7:0]data_out);
reg [3:0]SW_Key_buf;
always@(*)
if(MemRead)
begin
case (addr)
32'h0:outp = SW_Key[0];
32'h1:outp = SW_Key[1];
32'h2:outp = SW_Key[2];
32'h3:outp = SW_Key[3];
default:outp = 0 ;
endcase
end
always@(negedgeReset_n or posedge Clock)
if(Reset_n== 1'b0)
begin
SW_Key_buf <= 1;
end
elseif(MemWrite)
begin
case (addr)
32'h4:SW_Key_buf[0] <= data_in[0];
32'h5:SW_Key_buf[1] <= data_in[0];
32'h6:SW_Key_buf[2] <= data_in[0];
32'h7:SW_Key_buf[3] <= data_in[0];
default:;
endcase
end
MIPS_RESPONDER u1(.sys_clk(Clock),
.rst_n(Reset_n),
.key_0(SW_Key_buf[0]),
.key_1(SW_Key_buf[1]),
.key_2(SW_Key_buf[2]),
.host_key(SW_Key_buf[3]),
.chip_select(seg_com),
.seg_data(data_out));
Endmodule

求大手帮我解释一下呀~~