vhdl 程序编的闹钟系统的预置寄存器部分有如下错误帮忙看下谢谢
eda吧
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level 2
2046loop 楼主
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.P_ALARM.ALL;
ENTITY KEYBUFFER IS
PORT(KEY:IN STD_LOGIC;
CLK:IN STD_LOGIC;
RESET:IN STD_LOGIC;
KEYNUM:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
NEW_TIME:OUT T_CLOCK_TIME);
END ENTITY KEYBUFFER;
ARCHITECTURE ART OF KEYBUFFER IS
SIGNAL N_T:T_CLOCK_TIME;
SIGNAL CNT:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL TEMP:BIT_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK) IS
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
IF CNT=9 THEN
CNT<="0000";
ELSE
CNT<=CNT+'1';
END IF;
END IF;
KEYNUM<=CNT;
END PROCESS;
SHIFT:PROCESS(RESET,KEY) IS
BEGIN
IF (RESET='1') THEN
N_T(23 DOWNTO 20)<="0000";
N_T(19 DOWNTO 16)<="0000";
N_T(15 DOWNTO 12)<="0000";
N_T(11 DOWNTO 8)<="0000";
N_T(7 DOWNTO 4)<="0000";
N_T(3 DOWNTO 0)<="0000";
ELSIF (KEY'EVENT AND KEY='1') THEN
FOR I IN 5 DOWNTO 1 LOOP
N_T(I+18 DOWNTO 15+I)<=N_T(14+I DOWNTO 11+I);
END LOOP;
N_T(3 DOWNTO 0)<=TEMP;
END IF;
END PROCESS;
NEW_TIME<=N_T;
END ARCHITECTURE ART;
2015年01月05日 02点01分 1
level 2
2046loop 楼主
Error (10476): VHDL error at KEYBUFFER.vhd(41): type of identifier "TEMP" does not agree with its usage as "T_CLOCK_TIME" type
2015年01月05日 02点01分 2
level 3
就一类型转化错误,一个用的是bitvector,一个是stdlogicvector
2015年01月07日 20点01分 3
level 2
2046loop 楼主
谢谢
2015年01月09日 09点01分 4
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