module QDQ(K,S1,S2,S3,S4,S5,S6,S7,LED7S);
input K,S1,S2,S3,S4,S5,S6,S7;
output[3:0] LED7S;
reg[3:0] LED7S;
reg[7:1] Q;
reg ena;
always@(Q)
begin
ena=~(|Q);
end
always @(K or ens or S1 or S2 or S3 or S4 or S5 or S6 or S7);
begin
if(~K)Q='b0000000;
else if(ena & S1)Q='b0000001;
else if(ena & S2)Q='b0000010;
else if(ena & S3)Q='b0000100;
else if(ena & S4)Q='b0001000;
else if(ena & S5)Q='b0010000;
else if(ena & S6)Q='b0100000;
else if(ena & S7)Q='b1000000;
case(Q)
'b0000000:LED7S='b0000;
'b0000001:LED7S='b0001;
'b0000010:LED7S='b0010;
'b0000100:LED7S='b0011;
'b0001000:LED7S='b0100;
'b0010000:LED7S='b0101;
'b0100000:LED7S='b0110;
'b1000000:LED7S='b0111;
default:LED7S='b0000;
endcase
end
endmodule
Error (10170): Verilog HDL syntax error at QDQ.v(12) near text "begin"; expecting "endmodule"
Error (10112): Ignored design unit "qdq" at QDQ.v(1) due to previous errors
错误是出现什么啊