library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity color16 is
port(w: in std_logic;
q:out std_logic_vector(15 downto 0));
end color16;
architecture color of color16 is
signal u: std_logic_vector(18
downto 0);
signal v: std_logic;
signal ou: std_logic;
signal s: std_logic_vector (5
downto 0);
begin
p1: process(w)
begin
if w*event and w=*1* then
v<=u(18);
u<=u+1;
ou<=not v and u(18);
end if;
end process;
p2:process(ou)
begin
if ou*event and ou=*1* then
if s="101000" then
s<="000000";
else s<=s+1;
end if;
case s is
when "000000"=>q<="1000000010000000";
when "000001"=>q<="0100000001000000";
when "000010"=>q<="0010000000100000";
when "000011"=>q<="0001000000010000";
when "000100"=>q<="0000100000001000";
when "000101"=>q<="0000010000000100";
when "000110"=>q<="0000001000000010";
when "000111"=>q<="0000000100000001";
when "001000"=>q<="0000001000000010";
when "001001"=>q<="0000010000000100";
when "001010"=>q<="0000100000001000";
when "001011"=>q<="0001000000010000";
when "001100"=>q<="0010000000100000";
when "001101"=>q<="0100000001000000";
when "001110"=>q<="1000000010000000";
when "001011"=>q<="0001000000010000";
when "001100"=>q<="0010000000100000";
when "001101"=>q<="0100000001000000";
when "001110"=>q<="1000000010000000";
when "001111"=>q<="1100000011000000";
when "010000"=>q<="1110000011100000";
when "010001"=>q<="1111000011110000";
when "010010"=>q<="1111100011111000";
when "010011"=>q<="1111110011111100";
when "010100"=>q<="1111111011111110";
when "010101"=>q<="1111111111111111";
when "010110"=>q<="1111111011111110";
when "010111"=>q<="1111110011111100";
when "011000"=>q<="1111100011111000";
when "011001"=>q<="1111000011110000";
when "011010"=>q<="1110000011100000";
when "011011"=>q<="1100000011000000";
when "011100"=>q<="1000000010000000";
when "011101"=>q<="1111111111111111";
when "011110"=>q<="0000000000000000";
when "011111"=>q<="1000000110000001";
when "100000"=>q<="1100001111000011";
when "100001"=>q<="1110011111100111";
when "100010"=>q<="1111111111111111";
when "100011"=>q<="1110011111100111";
when "100100"=>q<="1110011111100111";
when "100101"=>q<="1100001111000011";
when "100110"=>q<="1000000110000001";
when "100111"=>q<="0000000000000000";
when "101000"=>q<="1111000000001111";
when "101001"=>q<="0000111111110000";
when others=>null;
end case;
end if;
end process;
end color;
错误如下：
Error (10321): VHDL error at color16.vhd(46): choice ""001011"" overlaps with a previous choice
Error (10321): VHDL error at color16.vhd(47): choice ""001100"" overlaps with a previous choice
Error (10321): VHDL error at color16.vhd(48): choice ""001101"" overlaps with a previous choice
Error (10321): VHDL error at color16.vhd(49): choice ""001110"" overlaps with a previous choice
Error: Can*t elaborate top-level user hierarchy
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 5 errors, 0 warnings
Error: Peak virtual memory: 292 megabytes
Error: Processing ended: Sun Nov 16 21:46:51 2014
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 7 errors, 0 warnings
求大神帮忙看下是哪里的问题

大神大神你在哪里？我需要你们。。。

case里面的情况重复了，检验值重复出现了001011