level 6
liujing5118
楼主
在网吧，只好让各位要看的进这连接，在页面中间有详细的定义哦http://bbs.52hardware.com/viewthread.php?action=printable&tid=106013
2008年01月22日 09点01分
1
倍频也能改？晕倒
2008年01月22日 09点01分
level 6
liujing5118
楼主
2
level 0
level 1
level 6
level 1
level 0
这个应该是旧款的VRM8.4电压标准，就是铜矿、赛羊1用的。图拉丁要求主板采用VRM8.5标准，重新定义了电压针脚信号，VRM8.5的电压信号有5根脚，共有32种组合，跨度为0.25伏，最低为1.05伏，最高为1.825伏。凡是支持图拉丁的主板都是这副德性，因此不能支持电压为2伏的赛羊1，铜矿核心的cpu要加电压也很困难（默认电压1.75，最高只能加到1.825）。前面有人说通过改针脚去加电压，对815epb主板来说也是笑话，因为不管你怎么改针脚，信号都是这32种组合中的一种，凡是采用VRM8.5标准的主板必然会把它翻译到1.05~1.825这个区间上。正如有一个英语单词要查词典翻译成中文，那么不管它是什么词，翻译出来的意思必然是词典中包含的内容，而不可能翻译出词典里没有的东西。
2008年02月13日 08点02分
12
level 0
Table 3. Voltage Identification Definition 1VID25mV VID3 VID2 VID1 VID0 VccCORE0 0 1 0 0 1.051 0 1 0 0 1.0750 0 0 1 1 1.101 0 0 1 1 1.1250 0 0 1 0 1.151 0 0 1 0 1.1750 0 0 0 1 1.201 0 0 0 1 1.2250 0 0 0 0 1.251 0 0 0 0 1.2750 1 1 1 1 1.301 1 1 1 1 1.3250 1 1 1 0 1.351 1 1 1 0 1.3750 1 1 0 1 1.401 1 1 0 1 1.4250 1 1 0 0 1.451 1 1 0 0 1.4750 1 0 1 1 1.501 1 0 1 1 1.5250 1 0 1 0 1.551 1 0 1 0 1.5750 1 0 0 1 1.601 1 0 0 1 1.6250 1 0 0 0 1.651 1 0 0 0 1.6750 0 1 1 1 1.701 0 1 1 1 1.7250 0 1 1 0 1.751 0 1 1 0 1.7750 0 1 0 1 1.801 0 1 0 1 1.825NOTES:1. 0 = Processor pin connected to VSS.1 = Open on processor; may be pulled up to TTL VIH (3.3V max) on baseboard.The VID pins should be pulled up to a 3.3 V level. This may be accomplished with pull-ups internal to the voltage regulator, which ensures valid VID pull-up voltage during Power-up andPower-down sequences. If external resistors are used for the VID[3:0, 25mV] signal, the power source must be guaranteed to be stable when the supply to the voltage regulator is stable. Thisprevents the possibility of the processor supply going above the specified VCCCORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC converter, this can beaccomplished by using the input voltage to the converter for the VID line pull-ups. A resistor equal to 1 KΩ may be used to connect the VID signals to the voltage regulator input.Note: Intel requires that designs utilize VRM 8.5 and not VRM 8.4 specifications to meet the Pentium III processor based on 0.13 micron process requirements.To re-emphasize, VRM 8.5 introduces two new signals [VID25mV and VTT_PWRGD] that is utilized by the Pentium III processor based on 0.13 micron process and platform. Ignoring and not connecting these two new pins, as documented in the Platform Design Guidelines, will prevent the Pentium III processor based on 0.13 micron process from operating at the specified voltage levelsand core frequency. Figure 6 provides a high-level interconnection schematic. Refer to the VRM 8.5 DC-DC Converter Design Guideline and the appropriate Platform Design Guidelines for further detailed information on the voltage identification and bus select implementation. Refer to Figure 14 for VID power-up sequence and timing requirements.
2008年02月13日 09点02分
13
level 6
level 6
liujing5118
楼主
请问谁知道这一点几的核心电压降/温压电是在主板上,还是在U内部?要是这在主板上,而处理器只是用这些脚告诉其使用的电压,那我们完全可以"自由发挥"啊
2008年02月13日 23点02分
15
level 6
level 6
level 6