level 5
观海听涛nice
楼主
module LorenzChaos2(clk,rst,out_en,daclk,x,y,z);
/*
1. 16 bits structure: 1bit(signed),5 bits(integer),10 bits(fraction)
2. 32 bits structure: 1bit(signed),5 bits(integer),26 bits(fraction)
3. 64 bits results ofmult: 2 bits(signed),9 bits(integer),53 bits(fraction)
*/
parameterXYZ_WIDTH=32;
parameterTMP_WIDTH=64;
parameterDAC_WIDTH=12; // 12bits DAC
input clk,rst;
output reg [DAC_WIDTH-1:0]x; //out to DAC
output reg [DAC_WIDTH-1:0]y;
output reg [DAC_WIDTH-1:0]z;
output daclk,out_en;
reg daclk,out_en;
reg signed[XYZ_WIDTH-1:0] x0=32'b0_00000_00110011001100110011000000; //0.20
reg signed[XYZ_WIDTH-1:0] y0=32'b0_00000_00011001100110011001100000; //0.10
reg signed[XYZ_WIDTH-1:0] z0=32'b0_00000_00100110011001100110000000; //0.15
reg signed[XYZ_WIDTH-1:0] a =32'b0_11100_00000000000000000000000000; // 28
reg signed[XYZ_WIDTH-1:0] b =32'b0_01100_00000000000000000000000000; // 12
reg signed[XYZ_WIDTH-1:0] c =32'b0_01010_00000000000000000000000000; // 10
regsigned[XYZ_WIDTH-1:0] x_offset =32'b0_00000_10000000000000000000000000; // offset value is 0.5, all results add0.5, in order to avoid negative value.
regsigned[XYZ_WIDTH-1:0] y_offset =32'b0_00000_10000000000000000000000000;
regsigned[XYZ_WIDTH-1:0] z_offset =32'b0_00000_10000000000000000000000000;
reg signed[XYZ_WIDTH-1:0] dx; // variables on the left of Lorenzequation
reg signed[XYZ_WIDTH-1:0] dy;
reg signed[XYZ_WIDTH-1:0] dz;
reg signed[XYZ_WIDTH-1:0] dx1; // variables on the left of Lorenzequation
reg signed[XYZ_WIDTH-1:0] dy1;
reg signed[XYZ_WIDTH-1:0] dz1;
reg signed[XYZ_WIDTH-1:0] fx; // temp for f(),where f() is the right ofLorenz equation
reg signed[XYZ_WIDTH-1:0] fy; //for detail,please refer to 2orders of R-K algorithm
reg signed[XYZ_WIDTH-1:0] fz;
reg signed[XYZ_WIDTH-1:0] fx_add_dx; // temp for operation: f()+dx
reg signed[XYZ_WIDTH-1:0] fy_add_dy; // for detail,please refer to2orders R-K algorithm
reg signed[XYZ_WIDTH-1:0] fz_add_dz;
reg signed[XYZ_WIDTH-1:0] x_tmp;
reg signed[XYZ_WIDTH-1:0] y_tmp;
reg signed[XYZ_WIDTH-1:0] z_tmp;
reg signed[TMP_WIDTH-1:0] zz; // z*z
reg signed[TMP_WIDTH-1:0] zz_mult_64; // z*z*64
reg signed[TMP_WIDTH-1:0] er_mult_yzz; // 2*y*z*z
reg signed[TMP_WIDTH-1:0] er_mult_yzz_mult_64; //2*y*z*z*64
reg signed[TMP_WIDTH-1:0] shi_mult_xz; // 10*x*z
reg signed[TMP_WIDTH-1:0] shi_mult_xz_mult_64; //10*x*z*64
reg signed[TMP_WIDTH-1:0] wu_mult_yy; // 5*y*y
reg signed[TMP_WIDTH-1:0] wu_mult_yy_mult_64;// 5*y*y*64
regsigned[TMP_WIDTH-1:0] fu_mult_cz; // -c*z
regsigned[TMP_WIDTH-1:0] fu_mult_ax; // -a*x
regsigned[TMP_WIDTH-1:0] by; //b*y
reg signed[TMP_WIDTH-1:0]fu_mult_ax_sub_er_mult_yzz_mult_64; // -ax-2yz^2
regsigned[TMP_WIDTH-1:0] by_add_shi_mult_xz_mult_64; //by+10xz
regsigned[TMP_WIDTH-1:0] fu_mult_cz_add_wu_mult_yy_mult_64; //-cz+5y^2
regsigned[TMP_WIDTH-1:0] dy_extend;
reg [3:0]state;
reg current_step;
reg next_step;
parameter s0=0,
s1=1,
s2=2,
s3=3,
s4=4,
s5=5,
s6=6,
s7=7,
s8=8,
s9=9;
