library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jid is
port(clk,clr:in std_logic;
shi:out std_logic_vector(3 downto 0);
ge:out std_logic_vector(3 downto 0);
dx:out std_logic_vector(2 downto 0);
nb:out std_logic_vector(2 downto 0)
);
end jid;
architecture one of jid is
TYPE fsm is(s0,s1,s2,s3);
signal cst,nst:fsm;
signal q1:std_logic_vector(3 downto 0);
signal q2:std_logic_vector(3 downto 0);
signal n1:std_logic_vector(2 downto 0);
signal n2:std_logic_vector(2 downto 0);
begin
process(clr,clk,cst)
begin
if clr='0' then cst<=s0;
elsif clk='1' and clk'event then cst<=nst;end if;
case cst is
when s0=>n1<="100";n2<="001";q1<="0011";q2<="0000";
if (q1="0000" and q2="0000") then nst<=s1;
elsif q2="0000" then q1<=q1-1;q2<=q2-1;
else q2<=q2-1;
end if;
when s1=>n1<="100";n2<="010";q1<="0000";q2<="0101";
if (q1="0000" and q2="0000") then nst<=s2;
else q2<=q2-1;
end if;
when s2=>n1<="001";n2<="100";q1<="0011";q2<="0000";
if (q1="0000" and q2="0000") then nst<=s3;
elsif q2="0000" then q1<=q1-1;q2<=q2-1;
else q2<=q2-1;
end if;
when s3=>n1<="100";n2<="010";q1<="0000";q2<="0101";
if (q1="0000" and q2="0000") then nst<=s0;
else q2<=q2-1;
end if;
when others=>null;
end case;
end process;
shi<=q1;ge<=q2;dx<=n1;nb<=n2;
end one;
大神们，这是我自己写的，题目要求做交通灯的状态图，有4个状态，我这样写，一直在s0状态。不跳到s2状态，为什么