library ieee;
use ieee.std_logic_1164.all;
entity top is
port(clk:in std_logic;
rst_n:in std_logic;
dout:out std_logic_vector(7 downto 0);
bar_en:out std_logic);
end top;
architecture behv of top is
component div is
port(clk:in std_logic;
clk_out:out std_logic);
end component;
component deng is
port(clk:in std_logic;
rst_n:in std_logic;
dout:out std_logic_vector(7 downto 0));
end component;
signal clk_div:std_logic;
begin
bar_en<='1';
inst_div:div port map (clk=>clk,clk_out=>clk_div);
inst_deng:deng port map (clk=>clk_div,rst_n=>rst_n,dout=>dout);
end behv;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div is
port(clk: in std_logic;
clk_out: out std_logic);
end div;
architecture behv of div is
signal cnt : std_logic_vector(22 downto 0);
signal clk_temp :std_logic;
constant PRD : integer := 4999999;
begin
process(clk)
begin
if clk'event and clk='1'then
if cnt = PRD then
cnt <=( others => '0');
clk_temp <= not clk_temp;
else
cnt <= cnt+1;
end if;
end if;
end process;
clk_out<=clk_temp;
end behv;
library ieee;
use ieee.std_logic_1164.all;
entity deng is
port(clk: in std_logic;
rst_n: in std_logic;
dout: out std_logic_vector(7 downto 0) );
end deng;
architecture behv of deng is
type FSN_ST is (IDLE,STATE1,STATE2,STATE3,STATE4,
STATE5,STATE6,STATE7,STATE8);
signal state, NextState : FSN_ST;
begin
process(clk,rst_n)
begin
if(rst_n='0')then
state<=IDLE;
elsif(clk'event and clk = '1')then
state<=NextState;
end if;
end process;
process(state,rst_n)
begin
case state is
when IDLE =>
if(rst_n = '0')then
NextState<=IDLE;
else
NextState<=STATE1;
end if;
when STATE1 => NextState <=STATE2;
when STATE2 => NextState <=STATE3;
when STATE3 => NextState <=STATE4;
when STATE4 => NextState <=STATE5;
when STATE5 => NextState <=STATE6;
when STATE6 => NextState <=STATE7;
when STATE7 => NextState <=STATE8;
when STATE8 => NextState <=STATE1;
when others => NextState <=IDLE;
end case;
end process;
process(clk)
begin
if(clk'event and clk = '1')then
case NextState is
when IDLE => dout <="00000000";
when STATE1 => dout <="00000001";
when STATE2 => dout <="00000010";
when STATE3 => dout <="00000100";
when STATE4 => dout <="00001000";
when STATE5 => dout <="00010000";
when STATE6 => dout <="00100000";
when STATE7 => dout <="01000000";
when STATE8 => dout <="10000000";
when others => dout <="00000000";
end case;
end if;
end process;
end behv;