library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity weideng is
port (clk:IN STD_LOGIC;
L:IN STD_LOGIC;
R:IN STD_LOGIC;
Y:IN STD_LOGIC;
S:IN STD_LOGIC;
light1:out std_logic_vector(2 downto 0);
light2:out std_logic_vector(2 downto 0);
light3:out std_logic_vector(2 downto 0);
light4:out std_logic_vector(2 downto 0));
end;
architecture art of weideng is
signal cut1:std_logic_vector(27 downto 0);
signal nclk:std_logic;
signal cnt:std_logic_vector(1 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
cnt1<=cnt1+1;
if cnt1=x "2faf080" then
cnt1=x "0000000";
nclk<='1';
else nclk<='0';
end if;
end process;
process(nclk)
begin
if nclk'event and nclk='1'then
cnt<=cnt+1;
if cnt="10" then cnt<="0";
end if;
end if;
end process;
uu1:process(clk,L,S,Y,R,cnt)
begin
if clk'event and clk='1'then
if L='1'then
case cnt is
when "00"=>light1<="001";
when "01"=>light1<="010";
when "10"=>light1<="100";
when others=>NULL;
end case;
else if L ='0'then
case cnt is
when "00"=>light1<="000";
when "01"=>light1<="000";
when "10"=>light1<="000";
when others=>NULL;
end case;
end if;
end if;
if S='1'then
case cnt is
when "00"=>light4<="011";
when "01"=>light4<="101";
when "10"=>light4<="110";
when others=>NULL;
end case;
else if S='0'then
case cnt is
when "00"=>light4<="000";
when "01"=>light4<="000";
when "10"=>light4<="000";
when others=>NULL;
end case;
end if;
end if;
if Y='1'then
case cnt is
when "00"=>light3<="011";
when "01"=>light3<="101";
when "10"=>light3<="110";
when others=>NULL;
end case;
else if y='0'then
case cnt is
when "00"=>light3<="000";
when "01"=>light3<="000";
when "10"=>light3<="000";
when others=>NULL;
end case;
end if;
end if;
if R='1'then
case cnt is
when "00"=>light2<="011";
when "01"=>light2<="101";
when "10"=>light2<="110";
when others=>NULL;
end case;
else if y='0'then
case cnt is
when "00"=>light2<="000";
when "01"=>light2<="000";
when "10"=>light2<="000";
when others=>NULL;
end case;
end if;
end if;
end if;
end process;
end art;
为什么说2FAF080数据不对哪位帮忙看先