1.LIBRARY IEEE;
2.USE IEEE.STD_LOGIC_1164.ALL;
3.ENTITY mux41 IS
4.PORT(s1,s2: IN STD_LOGIC;
5.a,b,c,d: IN STD_LOGIC;
6.z:OUT STD_LOGIC;);
7.END ENTITY mux41;
8. ARCHITECTURE activ OF mux41 IS
9. SIGNAL s: STD_LOGIC_VECTOR(1 DOWNTO 0);
11.s<=s1 & s2;
12.PROCESS(s,a,b,c,d)
14.CASE s IS
15.WHEN “00” =>z<=a;
16.WHEN “01 ”=>z<=b;
17.WHEN “10 ”=>z<=c;
18.WHEN “ 11 ”=>z<=d;
19.WHEN OTHERS =>z<= ’X ;
20.END CASE;
21.END PROCESS;
22.END activ;