1L du熊

NAND 的 op R & W
FC cmd到data interrupt forbidden
=> FC 需要 BUFFR & BUFFW
=> cmd & data 同步?

cache L1 L2 L3 ctrl很不方便=3=
+ MIG39...RAM...
都TM怪FC!
DDR RAM BUFF?
DDR BUFF RAM?
..............................1............................
data multi-layer delay? 大丈夫？
少女思考加速发动ing

BUFFR BUFFW 与cmd 同步率100% => FC data trans solved
NAND <--> BUFF priority HIGH
BUFF <--> RAM priority MID
RAM <--> DDR priority LOW
---------------------------------------------------------
BANDWIDTH? --

要是量子计算机就好了 (￣３￣)a
back -> synchronous puzzle
solution: null
cmd_next timing hard to archieve
------------------------------
摔！ 不然要BUFF干嘛！
------------------------------
back -> timing trick
R P E
E null
R short -> during busy or ready?
P long -> must ready first
=> ready...OK

NEXT
BUFF <--> RAM puzzle:
NAND -> BUFF CANNOT BE INTERRUPTED
BUFF -> NAND CANNOT BE INTERRUPTED
RAM -> BUFF CAN BE INTERRUPTED
BUFF -> RAM CAN BE INTERRUPTED
--------------------------------------
啊！枣恭介大人！@///@
--------------------------------------
5L 不对了...
case R0 R0 R0
无缝的话data->BUFF来不及的样子
=> when busy BUFF data -> RAM
when trans NAND data -> BUFF
DONE!

NEXT
RAM DEEPTH - OK
BUFF WIDTH - OK
RAM TRANS RATE - OK
BUFF TRANS RATE - OK
DMA CTRL - HARD
SPEED CTRL - HARD
------------------------------
DMA CTRL LOGIC:
addr 16 bit[max] need to be revised
REQ signal
roration - -?

puzzle ex:
FIFO or BUFF?
either syn
BUFF asyn
------------------------------
RAM?
sequential NULL
schedule randomly NEED
------------------------------
大概这样的感觉
图片来自: conanandai100的百度相册

Started : "Synthesize - XST".Running xst...Command Line: xst -intstyle ise -ifn "E:/Jormangandr/BUFF/dragonbuff/DRAGONBUFF.xst" -ofn "E:/Jormangandr/BUFF/dragonbuff/DRAGONBUFF.syr"Reading design: DRAGONBUFF.prj
=========================================================================* HDL Parsing *=========================================================================Parsing VHDL file "E:\Jormangandr\BUFF\dragonbuff\Buffer.vhd" into library workParsing entity <DRAGONBUFF>.Parsing architecture <Behavioral> of entity <dragonbuff>.
=========================================================================* HDL Elaboration *=========================================================================
Elaborating entity <DRAGONBUFF> (architecture <Behavioral>) from library <work>.
=========================================================================* HDL Synthesis *=========================================================================Process interrupted by the user
Process "Synthesize - XST" did not complete

这是个奇怪的地方

很明显，两个BUFF不能同时满足NAND和DDR，需要R和W分开来，开掉重练吧

Xst:3218 - HDL ADVISOR - The RAM <Mram_BUFF> will be implemented on LUTs
either because you have described an asynchronous read or because of currently
unsupported block RAM features. If you have described an asynchronous read,
making it synchronous would allow you to take advantage of available block RAM
resources, for optimized device usage and improved timings. Please refer to your
documentation for coding guidelines.

reg r1 = 0;
reg r2 = 0;
assign dataout = r1 ^ r2;
always @ (posedge clk)
if (R | S)
begin
r1 <= S;
end
else
begin
r1 <= datain ^ r2;
end
always @ (negedge clk)
if (R | S)
begin
r2 <= 0;
end
else
begin
r2 <= datain ^ r1;
end