library ieee;
use ieee.std_logic_1164.all;
entity qdq is
port(a:in std_logic;
b:in std_logic_vector(2 downto 0);
y:out std_logic_vector(6 downto 0));
end entity; architecture bhv of qdq is
signal lock:std_logic;
signal n:std_logic;
begin
process(a,lock)
begin
if(a='0')then
y<="000";
lock<='0';
if a'event and a='1'then
n<=n-1;
end if;
elsif (lock='0')then
case b is
when "100"=>y<="100";lock<='1';
when "010"=>y<="010";lock<='1';
when "001"=>y<="001";lock<='1';
when others=>y<="000";
end case;
end if;
end process;
process(n)
begin
case n is
when"1001"=>y<="1101111";
when"1000"=>y<="1111111";
when"0111"=>y<="0000111";
when"0110"=>y<="1111101";
when"0101"=>y<="1101101";
when"0100"=>y<="1100110";
when"0011"=>y<="1001111";
when"0010"=>y<="1011011";
when"0001"=>y<="0000110";
when"0000"=>y<="0111111";
when others=> null;
end case;
end process;
end bhv;