`timescale 1 ns / 1 ps
module seven_seg ( rst ,clk ,DIG ,Y );
input rst ;wire rst ;input clk ;wire clk ;
output [7:0] DIG ;wire [7:0] DIG ;output [7:0] Y ;wire [7:0] Y ;
reg clkout ;reg [31:0]cnt; reg [2:0]scan_cnt ; reg [3:0]A ;parameter period= 100000;
assign Y = {1'b1,(~Y_r[6:0])};assign DIG =~DIG_r;reg [6:0] Y_r;reg [7:0] DIG_r ;//}} End of automatically maintained section
always @( posedge clk or negedge rst) //分频50Hzbegin if (!rst)cnt <= 0 ;else begin cnt<= cnt+1;if (cnt== (period >> 1) - 1) //设定周期时间的一半clkout <= #1 1'b1;else if (cnt == period - 1)//设定的周期时间begin clkout <= #1 1'b0; cnt <= #1 'b0; end endend
always @(posedge clkout or negedge rst) // begin if (!rst)scan_cnt <= 0 ;else scan_cnt <= scan_cnt + 1; endalways @( scan_cnt) //数码管选择begin case ( scan_cnt )3'b000 : begin DIG_r <= 8'b0000_0001;A <= 1; end3'b001 : begin DIG_r <= 8'b0000_0010;A <= 3; end3'b010 : begin DIG_r <= 8'b0000_0100;A <= 5; end3'b011 : begin DIG_r <= 8'b0000_1000;A <= 7; end3'b100 : begin DIG_r <= 8'b0001_0000;A <= 9; end3'b101 : begin DIG_r <= 8'b0010_0000;A <= 11; end3'b110 : begin DIG_r <= 8'b0100_0000;A <= 13; end3'b111 : begin DIG_r <= 8'b1000_0000;A <= 15; end default : begin DIG_r <= 8'b0000_0000;A <= 0; end endcaseend
always @ ( A ) //译码begin case (A )0: Y_r = 7'b0111111; // 01: Y_r = 7'b0000110; // 12: Y_r = 7'b1011011; // 23: Y_r = 7'b1001111; // 34: Y_r = 7'b1100110; // 45: Y_r = 7'b1101101; // 56: Y_r = 7'b1111101; // 67: Y_r = 7'b0100111; // 78: Y_r = 7'b1111111; // 89: Y_r = 7'b1100111; // 910: Y_r = 7'b1110111; // A11: Y_r = 7'b1111100; // b12: Y_r = 7'b0111001; // c13: Y_r = 7'b1011110; // d14: Y_r = 7'b1111001; // E15: Y_r = 7'b1110001; // Fdefault: Y_r = 7'b0000000;endcaseendendmodule