部分展示。就是针对ping-pong双fifo控制。我想读写控制分离，用ping/pong_receive和ping/pong_send来控制什么时候可写可读。但是会存在多驱动问题。有没有更好的设计思路 。
always @(posedge clk or negedge rstn)
begin
if(!rstn) begin
ping_receive <= 1'b0;
ping_send <= 1'b0;
end
begin
case (wr_state)
PING:begin
if(to_output_en) begin
stream_data_outfifo_ping[to_output_point] <= {rounded_I,rounded_Q};
end
if(to_output_point == FIFO_LENGTH-1) begin
ping_receive <= 0;
ping_send <= 1;
end
end
PONG:begin
if(to_output_en) begin
stream_data_outfifo_pong[to_output_point] <= {rounded_I,rounded_Q};
end
if(to_output_point == FIFO_LENGTH-1) begin
pong_receive <= 0;
pong_send <= 1;
end
end
endcase
end
end
//M00的寄存器可以更新时
assign rd_en = m_tvalid && m_tready;
always @(posedge clk)
begin if(!rstn) begin
m_tvalid <= 0;
end else if(rd_en) begin
case (rd_state)
PING: begin
m_data <= stream_data_outfifo_ping[m_tdata_point];
ping_send <= 0;
ping_receive <= 1;
end
PONG: begin
m_data <= stream_data_outfifo_pong[m_tdata_point];
pong_send <= 0;
pong_receive <= 1;
end
endcase
end
end