tracy的样子的个人资料 - RAT

tracy的样子 tracy的样子

关注数: 6 粉丝数: 17 发帖数: 879 关注贴吧数: 6

想考研本校，有木有可以加的qq群……… 想考研本校，有木有可以加的qq群………

出个fpga开发版 qq307840790 xilinx的板子

想出手一块fpga开发版，xilinx的有木有要的嗯？早的话307840790

我不信在学校里没人要fpga开发版。我不信在学校里没人要fpga开发版。

求个课件，测控的精密仪器电路（苏燕辰老师的），测控网络技术（王雪梅老师的）

求问贵校校医院是不是有个叫董建华的老教授求老教授的坐诊时间和地点，感激不尽啊

学长送点东西剩下这两了，要的话自己来取宿舍号126002

求个收费书的电话～··

学长出一副麻将送插排

今年的毕业E册是不是有问题啊？？怎么一点下一页就黑了啊～～～～～～～～～～～·

学长出东西了～～电磁炉（送锅碗瓢盆和调料），电风扇，吹风，盗版高阶牛津字典各种书籍。。。。。。

出个单片机开发板有人联系就上图，硬件东西很全

听说学校EDA大神很多哦，能证明你是么？求解答疑问 VHDL编写的 library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; entity filter is port( clk,reset :in std_logic; sample_in :in signed (7 downto 0); result_out :out signed(20 downto 0)); end filter; architecture behave of filter is type coef_arr is array(0 to 18) of signed (7 downto 0); constant coefs: coef_arr:=coef_arr'("10000101","00000100","10000101","10001001","10000001","00000000","10001111","10001101","00011000","00110000","00011000",10001101","10001111","00000000","10000001","10001001","10000101","00000100","10000101"); begin process(clk,reset) type shift_register is array (17 downto 0) of signed (7 downto 0); variable shift : shift_register; variable temp : signed(7 downto 0); variable mul_value :signed(15 downto 0); variable acc_value : signed (20 downto 0); begin if(reset='0')then for i in 0 to 17 loop shift(i):=(others=>'0'); end loop; result_out<=(others=>'0'); elsif (clk'event and clk='1')then temp:=sample_in; mul_value:=temp*coefs(0); acc_value:=conv_signed(mul_value,20); for i in 17 downto 0 loop mul_value:=shift(i)*coefs(i+1); acc_value:=acc_value+conv_signed(mul_value,20); shift(i+1):=shift(i); end loop; shift(0):=temp; result_out<=acc_value; ——————报错在此 end if; end process; end behave; 报错类型Error (10500): VHDL syntax error at cou.vhd(39) near text "process"; expecting ";", or an identifier ("process" is a reserved keyword), or "architecture"

听说学校EDA大神很多饿，敢不敢冒个泡求解答疑问 VHDL写的一段程序 library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; entity filter is port( clk,reset :in std_logic; sample_in :in signed (7 downto 0); result_out :out signed(20 downto 0)); end filter; architecture behave of filter is type coef_arr is array(0 to 18) of signed (7 downto 0); constant coefs: coef_arr:=coef_arr'("10000101","00000100","10000101","10001001","10000001","00000000","10001111","10001101","00011000","00110000","00011000",10001101","10001111","00000000","10000001","10001001","10000101","00000100","10000101"); begin process(clk,reset) type shift_register is array (17 downto 0) of signed (7 downto 0); variable shift : shift_register; variable temp : signed(7 downto 0); variable mul_value :signed(15 downto 0); variable acc_value : signed (20 downto 0); begin if(reset='0')then for i in 0 to 17 loop shift(i):=(others=>'0'); end loop; result_out<=(others=>'0'); elsif (clk'event and clk='1')then temp:=sample_in; mul_value:=temp*coefs(0); acc_value:=conv_signed(mul_value,20); for i in 17 downto 0 loop mul_value:=shift(i)*coefs(i+1); acc_value:=acc_value+conv_signed(mul_value,20); shift(i+1):=shift(i); end loop; shift(0):=temp; result_out<=acc_value; ——————报错在此 end if; end process; end behave; 报错类型Error (10500): VHDL syntax error at cou.vhd(39) near text "process"; expecting ";", or an identifier ("process" is a reserved keyword), or "architecture"

听说科大eda大神很多哦求解答疑问 library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; entity filter is port( clk,reset :in std_logic; sample_in :in signed (7 downto 0); result_out :out signed(20 downto 0)); end filter; architecture behave of filter is type coef_arr is array(0 to 18) of signed (7 downto 0); constant coefs: coef_arr:=coef_arr'("10000101","00000100","10000101","10001001","10000001","00000000","10001111","10001101","00011000","00110000","00011000",10001101","10001111","00000000","10000001","10001001","10000101","00000100","10000101"); begin process(clk,reset) type shift_register is array (17 downto 0) of signed (7 downto 0); variable shift : shift_register; variable temp : signed(7 downto 0); variable mul_value :signed(15 downto 0); variable acc_value : signed (20 downto 0); begin if(reset='0')then for i in 0 to 17 loop shift(i):=(others=>'0'); end loop; result_out<=(others=>'0'); elsif (clk'event and clk='1')then temp:=sample_in; mul_value:=temp*coefs(0); acc_value:=conv_signed(mul_value,20); for i in 17 downto 0 loop mul_value:=shift(i)*coefs(i+1); acc_value:=acc_value+conv_signed(mul_value,20); shift(i+1):=shift(i); end loop; shift(0):=temp; result_out<=acc_value; ——————报错在此 end if; end process; end behave; 报错类型Error (10500): VHDL syntax error at cou.vhd(39) near text "process"; expecting ";", or an identifier ("process" is a reserved keyword), or "architecture" 求解答

EDA大神在哪？求大神指导这段程序哪错了 library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all;package coeffs is type coef_arr is array(0 to 18) of signed (7 downto 0); constant coefs: coef_arr:=coef_arr'("10000101","00000100","10000101","10001001","10000001","00000000","10001111","10001101","00011000","00110000","00011000",10001101","10001111","00000000","10000001","10001001","10000101","00000100","10000101"); end coeffs; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.coeffs.all; entity filter is port( clk,reset :in std_logic; sample_in :in signed (7 downto 0); result_out :out signed(20 downto 0)); end filter; architecture behave of filter is begin process(clk,reset) type shift_register is array (18 downto 0) of signed (7 downto 0); variable shift : shift_register; variable temp : signed(7 downto 0); variable mul_value :signed(15 downto 0); variable acc_value : signed (20 downto 0); begin if(reset='0')then for i in 0 to 18 loop shift(i):=(others=>'0'); end loop; result_out<=(others=>'0'); else if (clk'event and clk='1')then temp:=sample_in; mul_value:=temp*coefs(0); acc_value:=conv_signed(mul_value,20); for i in 18 downto 0 loop mul_value:=shift(i)*coefs(i+1); acc_value:=acc_value+conv_signed(mul_value,20); shift(i+1):=shift(i); end loop; shift(0):=temp; result_out<=acc_value; end if; end if; end process; end behave;

热爱学习的孩子快来吧，出个单片机的开发板图暂时就不上了开发板功能比较齐全遥控器，双行显示器，彩屏显示器，点阵，步进电机，直流电机都有

万分感谢今天中午捡到我一卡通的同学当我从12号楼门卫那拿到一卡通的时候，瞬间感觉交大好有爱

求个电源适配器，坏了的也可以额~~~ 等待~~

求个笔记本电源适配器，坏了的也可以~~~~ rt 等待中~~~~

有木有人知道真气运行法？？这个玩意靠谱不？求解……

求个学校10年发的手表

陕西的汉子你们都准备什么时间回额

求一个学校发的手表

有没有签3+1的那个考试怎么考？？

求个学校以前发的手表男士的

有木有和我一样的，心里难受的要死却不想说！！

发现自己越来越寂寞了

求一套车辆机车方向的专业书已经有《机车总体及转向架》

怎么查个人学费交费明细

有木有前线铁路局的同学

12号楼的建环专业想不通你们在楼道里开毛party 吵死了无语

求个MP3 便宜一点的

那个3+1是怎么回事

有么有人知道3+1？？？

3+1你懂不？？？

签完之后突然感觉虚得很有么有

有么有人有北京铁路局的招聘处的电话额急求各位大神额

到底西安局好进不有没有学长现身说一哈

弱弱的问一哈有么有人知道西安铁路局招聘处的电话额

有木有人知道西安铁路局招聘处的电话额急求额

绿色和平曝美机构用中国儿童做转基因大米试验 http://tieba.baidu.com/mo/q/checkurl?url=http%3A%2F%2Fnews.qq.com%2Fa%2F20120831%2F001159.htm%3Fpgv_ref%3Daio2012%26ptlang%3D2052&urlrefer=eb20860cbbe4c1ccf636194f37ee1552 不知大家看了会怎么想

我勒个凑有没有了解西安地铁的 rt

我勒个凑学校有没有了解西安地铁的在线等待

一个正常的贴吧里水贴和质量帖是同事存在的貌似现在的贴吧，有质量的帖子很少了! 是大家都水了，还是大家把想说的话都藏在心里了？

那些来交大钓鱼的人越来越不像话了车子汽车都开到草坪上了鄙视后勤集团的主管

给我护的妹子都是10分，不给我护的都是0分

今天我又回交大了

22年的男吊求妹子带走看书着，突然就有了这想法

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