第100隻懶懶熊 第100隻懶懶熊
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modelSim error 求教 compiler能过 modelsim过不了 # Reading C:/altera/14.1/modelsim_ase/tcl/vsim/pref.tcl # do practice_run_msim_gate_verilog.do # if {[file exists gate_work]} { # vdel -lib gate_work -all # } # vlib gate_work # vmap work gate_work # Model Technology ModelSim PE vmap 10.3c Lib Mapping Utility 2014.09 Sep 20 2014 # vmap -modelsim_quiet work gate_work # Copying C:/altera/14.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # ** Warning: Copied C:/altera/14.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini. # Updated modelsim.ini. # # vlog -vlog01compat -work work +incdir+. {practice.vo} # Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014 # Start time: 23:52:57 on Feb 07,2015 # vlog -reportprogress 300 -vlog01compat -work work "+incdir+." practice.vo # -- Compiling module HW3_1 # # Top level modules: # HW3_1 # End time: 23:52:58 on Feb 07,2015, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # # vlog -vlog01compat -work work +incdir+C:/altera/project/db {C:/altera/project/db/HW3_1_t.v} # Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014 # Start time: 23:52:58 on Feb 07,2015 # vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/altera/project/db" C:/altera/project/db/HW3_1_t.v # -- Compiling module testbench # ** Warning: C:/altera/project/db/HW3_1_t.v(79): (vlog-2643) Unterminated string literal continues onto next line. # # # Top level modules: # testbench # End time: 23:52:58 on Feb 07,2015, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # # vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L altera_lnsim_ver -L cyclonev_ver -L lpm_ver -L sgate_ver -L cyclonev_hssi_ver -L altera_mf_ver -L cyclonev_pcie_hip_ver -L gate_work -L work -voptargs="+acc" HW3_1_t # vsim -gui -l msim_transcript -do "practice_run_msim_gate_verilog.do" # Start time: 23:52:58 on Feb 07,2015 # ** Error: (vsim-3170) Could not find 'C:/altera/project/simulation/modelsim/gate_work.HW3_1_t'. # # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./practice_run_msim_gate_verilog.do PAUSED at line 12 请问这个错该如何解决 求教
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