勇敢风风光光º的个人资料 - RAT

勇敢风风光光º 滴答声1234

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a19 pro geekbench ai跑分汇总 cpu提升三分之一 gpu提升100%以上 npu几乎不变

tensorflow cpu对比o1/8e/9k4 o1的cpu跑cpu的ai居然这么强部分子项强了两倍

o1这个温度有点高，接近50度了来自价值300万的视频

O1的geekbench ai出来了选择相同的NNAPI接口

这次玄戒首发量少的可怜只能在汽车融合店销售。疑似首发只有小米15s pro，平板目前都没有跑分泄漏，虽然已经备案了，但是目前没有看到跑分。

有viulkan跑分了

gpu也和9400差不多了

小米商城15第二天和13一个月销量持平

rosetta/prism/box64/exagear/fex/qemu转译avx2性能比较

windows on arm最新转译的指令集手头有一个8cx gen 3的机器，更新canary之后检测指令集如下： Snapdragon Compute Platform ARMv8 (64-bit) Family 8 Model D4B Revision 0, Qualcomm Technologies Inc HTT - Multicore CET - Supports Control Flow Enforcement Technology Kernel CET - Kernel-mode CET Enabled User CET - User-mode CET Allowed HYPERVISOR - Hypervisor is present VMX - Supports Intel hardware-assisted virtualization SVM - Supports AMD hardware-assisted virtualization X64 * Supports 64-bit mode SMX - Supports Intel trusted execution SKINIT - Supports AMD SKINIT SGX - Supports Intel SGX NX * Supports no-execute page protection SMEP - Supports Supervisor Mode Execution Prevention SMAP - Supports Supervisor Mode Access Prevention PAGE1GB - Supports 1 GB large pages PAE - Supports > 32-bit physical addresses PAT - Supports Page Attribute Table PSE - Supports 4 MB pages PSE36 - Supports > 32-bit address 4 MB pages PGE - Supports global bit in page tables SS - Supports bus snooping for cache operations VME - Supports Virtual-8086 mode RDWRFSGSBASE * Supports direct GS/FS base access FPU * Implements i387 floating point instructions MMX * Supports MMX instruction set MMXEXT - Implements AMD MMX extensions 3DNOW - Supports 3DNow! instructions 3DNOWEXT - Supports 3DNow! extension instructions SSE * Supports Streaming SIMD Extensions SSE2 * Supports Streaming SIMD Extensions 2 SSE3 * Supports Streaming SIMD Extensions 3 SSSE3 * Supports Supplemental SIMD Extensions 3 SSE4a - Supports Streaming SIMDR Extensions 4a SSE4.1 * Supports Streaming SIMD Extensions 4.1 SSE4.2 * Supports Streaming SIMD Extensions 4.2 AES * Supports AES extensions AVX * Supports AVX instruction extensions AVX2 * Supports AVX2 instruction extensions AVX-512-F - Supports AVX-512 Foundation instructions AVX-512-DQ - Supports AVX-512 double and quadword instructions AVX-512-IFAMA - Supports AVX-512 integer Fused multiply-add instructions AVX-512-PF - Supports AVX-512 prefetch instructions AVX-512-ER - Supports AVX-512 exponential and reciprocal instructions AVX-512-CD - Supports AVX-512 conflict detection instructions AVX-512-BW - Supports AVX-512 byte and word instructions AVX-512-VL - Supports AVX-512 vector length instructions FMA * Supports FMA extensions using YMM state MSR - Implements RDMSR/WRMSR instructions MTRR - Supports Memory Type Range Registers XSAVE * Supports XSAVE/XRSTOR instructions OSXSAVE * Supports XSETBV/XGETBV instructions RDRAND * Supports RDRAND instruction RDSEED - Supports RDSEED instruction CMOV * Supports CMOVcc instruction CLFSH * Supports CLFLUSH instruction CX8 * Supports compare and exchange 8-byte instructions CX16 * Supports CMPXCHG16B instruction BMI1 * Supports bit manipulation extensions 1 BMI2 * Supports bit manipulation extensions 2 ADX - Supports ADCX/ADOX instructions DCA - Supports prefetch from memory-mapped device F16C * Supports half-precision instruction FXSR * Supports FXSAVE/FXSTOR instructions FFXSR - Supports optimized FXSAVE/FSRSTOR instruction MONITOR - Supports MONITOR and MWAIT instructions MOVBE * Supports MOVBE instruction ERMSB - Supports Enhanced REP MOVSB/STOSB PCLMULDQ * Supports PCLMULDQ instruction POPCNT * Supports POPCNT instruction LZCNT * Supports LZCNT instruction SEP - Supports fast system call instructions LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode HLE - Supports Hardware Lock Elision instructions RTM - Supports Restricted Transactional Memory instructions DE - Supports I/O breakpoints including CR4.DE DTES64 - Can write history of 64-bit branch addresses DS - Implements memory-resident debug buffer DS-CPL - Supports Debug Store feature with CPL PCID - Supports PCIDs and settable CR4.PCIDE INVPCID - Supports INVPCID instruction PDCM - Supports Performance Capabilities MSR RDTSCP * Supports RDTSCP instruction TSC * Supports RDTSC instruction TSC-DEADLINE - Local APIC supports one-shot deadline timer TSC-INVARIANT * TSC runs at constant rate xTPR - Supports disabling task priority messages EIST - Supports Enhanced Intel Speedstep ACPI - Implements MSR for power management TM - Implements thermal monitor circuitry TM2 - Implements Thermal Monitor 2 control APIC - Implements software-accessible local APIC x2APIC - Supports x2APIC CNXT-ID - L1 data cache mode adaptive or BIOS MCE - Supports Machine Check, INT18 and CR4.MCE MCA - Implements Machine Check Architecture PBE - Supports use of FERR#/PBE# pin PSN - Implements 96-bit processor serial number PREFETCHW * Supports PREFETCHW instruction Maximum implemented CPUID leaves: 0000000D (Basic), 80000008 (Extended). Maximum implemented address width: 32 bits (virtual), 32 bits (physical). Processor signature: 00600F01 Logical to Physical Processor Map: *------- Physical Processor 0 -*------ Physical Processor 1 --*----- Physical Processor 2 ---*---- Physical Processor 3 ----*--- Physical Processor 4 -----*-- Physical Processor 5 ------*- Physical Processor 6 -------* Physical Processor 7 Logical Processor to Socket Map: ******** Socket 0 Logical Processor to NUMA Node Map: ******** NUMA Node 0 No NUMA nodes. Logical Processor to Cache Map: *------- Instruction Cache 0, Level 1, 32 KB, Assoc 4, LineSize 64 *------- Data Cache 0, Level 1, 32 KB, Assoc 4, LineSize 64 *------- Unified Cache 0, Level 2, 512 KB, Assoc 8, LineSize 64 ******** Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64 -*------ Instruction Cache 1, Level 1, 32 KB, Assoc 4, LineSize 64 -*------ Data Cache 1, Level 1, 32 KB, Assoc 4, LineSize 64 -*------ Unified Cache 2, Level 2, 512 KB, Assoc 8, LineSize 64 --*----- Instruction Cache 2, Level 1, 32 KB, Assoc 4, LineSize 64 --*----- Data Cache 2, Level 1, 32 KB, Assoc 4, LineSize 64 --*----- Unified Cache 3, Level 2, 512 KB, Assoc 8, LineSize 64 ---*---- Instruction Cache 3, Level 1, 32 KB, Assoc 4, LineSize 64 ---*---- Data Cache 3, Level 1, 32 KB, Assoc 4, LineSize 64 ---*---- Unified Cache 4, Level 2, 512 KB, Assoc 8, LineSize 64 ----*--- Instruction Cache 4, Level 1, 64 KB, Assoc 4, LineSize 64 ----*--- Data Cache 4, Level 1, 64 KB, Assoc 4, LineSize 64 ----*--- Unified Cache 5, Level 2, 1 MB, Assoc 8, LineSize 64 -----*-- Instruction Cache 5, Level 1, 64 KB, Assoc 4, LineSize 64 -----*-- Data Cache 5, Level 1, 64 KB, Assoc 4, LineSize 64 -----*-- Unified Cache 6, Level 2, 1 MB, Assoc 8, LineSize 64 ------*- Instruction Cache 6, Level 1, 64 KB, Assoc 4, LineSize 64 ------*- Data Cache 6, Level 1, 64 KB, Assoc 4, LineSize 64 ------*- Unified Cache 7, Level 2, 1 MB, Assoc 8, LineSize 64 -------* Instruction Cache 7, Level 1, 64 KB, Assoc 4, LineSize 64 -------* Data Cache 7, Level 1, 64 KB, Assoc 4, LineSize 64 -------* Unified Cache 8, Level 2, 1 MB, Assoc 8, LineSize 64 Logical Processor to Group Map: ******** Group 0

arm Mac mini性价比之外的另一评价维度：安静夜深人静，在构建不同系统的生成物时，x86主机总是呼啦呼啦的响，只要有一点负载，风扇立刻起飞，必须自己手动调节TDP或者风扇曲线才能降低风扇到非常安静的程度。 arm的mac mini几乎听不到风扇在响，安静在角落里充当媒体服务器，构建服务器，「网络交换机」，还有上网机。

8 Elite其他外围特性升级和变化根据官方Spec和8 Gen 3对比列出射频系统 + AI-enhanced performance improvements in power handling, coverage, latency, & QoS + AI-assisted mmWave beam management–mmWave (SA) range extension for CPE AI-based GNSS Location: Gen 2 -> Gen 3 Qualcomm® 5G PowerSave: Gen 4 -> Gen 5 Qualcomm® Smart Transmit™ technology with Snapdragon® Satellite support: Gen 4 -> Gen 5 + Fully integrated NB-NTN support Sub-6 Ghz: 4x4 MIMO -> 4x6 MIMO - HSPA/TD-SCDMA,CDMA,EV_DO + LAA,DSS + 5G New Calling support + Qualcomm(R) RF Uplink Optimization + Global 5G multi-SIM, including Qualcomm DSDA Gen 2 Bluetooth: 5.4 -> 6.0 + Integrated Ultra Wideband (UWB) • IEEE 802.15.4z, FiRA, CCC 影像系统 Engine for Visual Analytics 4.0, including hardware acceleration for iToF depth sensors: 1080p30 -> 4k60 DCG+VS 36 MP triple camera @ 30 FPS with Zero Shutter Lag 48 MP triple camera @ 30 FPS with Zero Shutter Lag Slow-mo: 720p960->1080P480 Segmentation photo and video processing:12 layers -> 250 layers 音频： + Qualcomm Aqstic Speaker Max GPU： Unreal Engine： - 5.3 Nanite on smartphones - e Chaos Physics Engine Adreno Frame Motion Engine:2.0->2.1 + Snapdragon Adaptive Game Configuration 安全： Truepic with C2PA for video and audio IP Protection for AI models

A18 pro的web子项居然不如8 gen 4 唯一大幅领先的是object detection

测试下mac15模拟avx2下的emeditor avx2模式可以打开，但是进程打开后处于未响应的状态，旧版rosetta无法打开avx2模式的，只能打开avx模式的。

gb6 单核3833了

8cx gen 2 wild life extreme比870强一点，1323分来自小米笔记本12.4 二合一，870参考socpk的分数1231分。 gpu是adreno 685

8cx gen 3的wild life extreme是2853分，和8+ gen1 差不多 gpu是Adreno 690，8 gen 2是3750左右，8 gen 2还是强

windows on arm运行移动端原神（woa

小米13上USB3.0了？看到闲聊站暗示上了，这次小米商城详情页没看到USB参数。

小米13 Pro的Compute分数opencl 8601 对比 8+提升三分之一 compute-5959376

微软开发包2023（8cx gen 3）跑分原生跑分Linux Hyper-V虚拟机跑分

Linux不需要arm也可以rosetta arm掌机用上rosetta+Proton 岂不是未来可期

A15的iOS16中speedometer有345分了 A15在iOS16.0.1m1 chrome 105safari 338手头没有8475的机子，notebookcheck这个好像不太准

继续挖掘A16的Geekbench分数兼统计上限单核最高 1887，同时也是多核最高 5445 id 17141095 v4单核 8069 多核 21367 id 16616113 Compute最高 15884 5458479 ML Inference TensorFlow Lite Core ML Inference Score 3160 ID 195499 TensorFlow Lite CPU Inference Score 999 id 195489 TensorFlow Lite GPU Inference Score 2484 id 195493

iOS16.0的Geekbench计算分和iOS15.X比起来有点异常 compare 5103510?baseline=5102784分数低好多，好几个子项明显弱于iOS15。X Sobel， Histogram Equalization， Depth of Field SFFT 这几个有50%甚至100%的差距

14标准版内存6GB cpu id 17157612

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